Increased miniaturization of components, greater packaging density of integrated circuits (“ICs”), higher performance, and lower cost are ongoing goals of the computer industry. Semiconductor package structures continue to advance toward miniaturization, to increase the density of the components that are packaged therein while decreasing the sizes of the products that are made therefrom. This is in response to continually increasing demands on information and communication products for ever-reduced sizes, thicknesses, and costs, along with ever-increasing performance.
These increasing requirements for miniaturization are particularly noteworthy, for example, in portable information and communication devices such as cellular phones, hands-free cellular phone headsets, personal data assistants (“PDA's”), camcorders, notebook computers, and so forth. All of these devices continue to be made smaller and thinner to improve their portability. Accordingly, large-scale IC (“LSI”) packages that are incorporated into these devices are required to be made smaller and thinner. The package configurations that house and protect LSI require them to be made smaller and thinner as well.
Many conventional semiconductor (or “chip”) packages are of the type where a semiconductor die is molded into a package with a resin, such as an epoxy molding compound. The packages have a lead frame whose leads are projected from the package body, to provide a path for signal transfer between the die and external devices. Other conventional package configurations have contact planar terminals or pads formed directly on the surface of the package. Such a conventional semiconductor package is fabricated through the following processes: a die-bonding process (mounting the semiconductor die onto the paddle of a lead frame), a wire-bonding process (electrically connecting the semiconductor die on the paddle to inner leads using lead frame wires), a molding process (encapsulating a predetermined portion of the assembly, containing the die, inner leads and lead frame wires, with an epoxy resin to form a package body), and a trimming process (completing each assembly as individual, independent packages).
The semiconductor packages, thus manufactured, are then mounted by matching and soldering the external leads or contact pads thereof to a matching pattern on a circuit board, to thereby enable power and signal input/output (“I/O”) operations between the semiconductor devices in the packages and the circuit board.
Different challenges arise from increased functionality integration and miniaturization. For example, a semiconductor product having increased functionality may be made smaller but may still be required to provide a large number of inputs/outputs (I/O). The size reduction increases the I/O density or decreases the I/O pitch for the integrated circuit package and its respective integrated circuit carriers.
The ever-increasing I/O density trend presents a myriad of manufacturing problems. Some of these problems reside in integrated circuit manufacturing realm, such as fine pitch connections and reliability of these connections. Others problems involve mounting these increase I/O density integrated circuits on carriers for packaging. Yet other problems reside in the realm of the printed circuit board or the system board that receives the integrated circuit package having the fine pitch I/O or a large number of I/Os in an ever-shrinking space.
An exemplary semiconductor package, well known in the electronics industry, is the quad flat package (“QFP”). QFP packages typically comprise a lead frame, such as a conductive sheet stamped and etched, with a semiconductor die having a multitude of bond pads mounted to the top side of the lead frame. Bond wires electrically connect the bond pads, of the semiconductor die, to a series of conductive lead fingers on the topside of the lead frame. Typically, the semiconductor die and the bond wires are encapsulated within a molding compound.
In order to reduce manufacturing costs, the electronics industry is increasing the usage of QFP packages. In the manufacturing process, many obstacles must be overcome to deliver extremely small packages with thinner and thinner profile in high volume while providing connectivity to a large number of I/O. Despite the trend towards miniaturization and thinner profile, more functions and more integrated circuits are continued to be packed into QFP packages.
Thus, a need still remains for an integrated circuit packaging system providing low cost manufacturing, improved yield, improved reliability, and high density I/O count. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.